Apparatus and method for early issue and recovery for a conditional load instruction having multiple outcomes

摘要

At least one instruction of a sequence of program instructions has a plurality of alternative outcomes including at least a first outcome that is independent of at least one operand and a second outcome that is dependent on the at least one operand. The at least one operand is a value generated by a preceding instruction in the sequence. The at least one instruction is issued for execution independently of when the at least one operand is generated by the preceding instruction. Recovery circuitry is provided to perform a recovery operation in the event that the second outcome is to be executed for the at least one instruction and the at least one operand has not been generated by the preceding instruction when the at least one instruction is to be executed by said instruction execution circuitry.

主权项

1. An apparatus for processing data under control of a sequence of program instructions, said apparatus comprising:
an instruction decoder for decoding said program instructions to generate decoded instructions, said program instructions including a conditional load instruction having a plurality of alternative outcomes, said alternative outcomes including at least a first outcome that is independent of at least one operand and a second outcome that is dependent on said at least one operand, said at least one operand being generated by a preceding instruction of said sequence of program instructions; instruction issuing circuitry for issuing said decoded instructions for execution, said instruction issuing circuitry configured to issue one of said decoded instructions corresponding to said conditional load instruction independently of when said at least one operand is generated by said preceding instruction; instruction execution circuitry for executing said decoded instructions issued by said instruction issuing circuitry, wherein said instruction execution circuitry is responsive to said one of said decoded instructions corresponding to said conditional load instruction to load a value from a memory to a destination register if a condition associated with said conditional load instruction is satisfied; and recovery circuitry for performing a recovery operation in the event that said second outcome is to be executed for said conditional load instruction and said at least one operand has not been generated by said preceding instruction when said one of said decoded instructions corresponding to said conditional load instruction is to be executed by said instruction execution circuitry.