Stress-based techniques for detecting an imminent read failure in a non-volatile memory array

摘要

A technique for detecting an imminent read failure in a non-volatile memory array includes applying a bulk read stress to a plurality of cells of the non-volatile memory array and determining whether the plurality of cells exhibit an uncorrectable error correcting code (ECC) read during an array integrity check at a margin read verify voltage level subsequent to the bulk read stress. The technique also includes providing an indication of an imminent read failure for the plurality of cells when the plurality of cells exhibit the uncorrectable ECC read during the array integrity check. In this case, the margin read verify voltage level is different from a normal read verify voltage level.

主权项

1. A method of detecting an imminent read failure in a non-volatile memory array, comprising:
applying a gate bias voltage, higher than a normal read verify voltage level, to a plurality of cells of the non-volatile memory array for a duration of time, wherein the normal read verify voltage level is a voltage level applied to a gate of a cell of the plurality of cells of the non-volatile memory array to determine a value stored by the cell; after the applying the gate bias voltage for the duration of time, determining whether the plurality of cells exhibit an uncorrectable error correcting code (ECC) read during an array integrity check at a margin read verify voltage level, wherein the margin read verify voltage level is either higher than the normal read verify voltage level for the plurality of cells or lower than the normal read verify voltage level for the plurality of cells; and providing an indication of an imminent read failure when the plurality of cells exhibit the uncorrectable ECC read during the array integrity check.