| 发明名称 | Divider circuit and division method | ||
| 摘要 | A divider circuit includes: a register which is configured of an even number of bits and in which a dividend data is stored. A shift operation section is configured to acquire a data stored in an upper bit portion of the register when the even number of bits of the register is equally divided to the upper bit portion and a lower bit portion, as a quotient data when the dividend data is divided by a maximum of a divisor data which can be expressed by a half of the even number of bits of the register. | ||
| 申请公布号 | US8977671(B2) | 申请公布日期 | 2015.03.10 |
| 申请号 | US201113324915 | 申请日期 | 2011.12.13 |
| 申请人 | Renesas Electronics Corporation | 发明人 | Tanaka Mihoko |
| 分类号 | G06F7/52;G06F7/535 | 主分类号 | G06F7/52 |
| 代理机构 | McGinn IP Law. Group, PLLC | 代理人 | McGinn IP Law. Group, PLLC |
| 主权项 | 1. A divider circuit comprising: a register comprising an even number of bits and in which a dividend data is stored; a shift operation section configured to acquire a data stored in an upper bit portion of said register when the even number of bits of said register is equally divided to said upper bit portion and a lower bit portion; and an error determining section configured to calculate a summation of said upper bit portion data and a data of said lower bit portion and determine said error data based on said summation; wherein said divider circuit provides a sum of the data stored in said upper bit portion and an error data as a quotient data when said dividend data is divided by a maximum of a divisor data which can be expressed by a half of the even number of bits of said register. | ||
| 地址 | Kawasaki-shi, Kanagawa JP | ||