Circuit design system and method of generating hierarchical block-level timing constraints from chip-level timing constraints

摘要

A system and method of designing an integrated circuit capable of deriving timing constraints for individual block-level circuits of an integrated circuit that are derived from the chip-level timing constraints and analysis. The block-level timing constraints are in the form of one or more logical timing constraint points at the input and output ports of block-level circuits. Each logical timing constraint points specifies a clock source used to clock data through the port, a delay parameter specifying data propagation delay backward from an input port and forward from an output port, and any timing exception associated with the data path. Using the logical timing constraint point, the circuit design system performs independent timing analysis and optimization of each block-level circuit. The system then reassembles the block-level circuits into a modified chip-level circuit for which timing closure can be achieved.

主权项

1. A circuit design system comprising:
a processor adapted to
receive a chip-level circuit design and chip-level timing constraints thereof;partition the chip-level circuit design into at least a first block-level circuit design and a second block-level circuit design, wherein the first block-level circuit design includes an output port, and the second block-level circuit design includes an input port to couple to the output port of the first block-level circuit design;determine a first logical timing constraint point for the output port of the first block-level circuit design from the chip-level timing constraints of the chip-level circuit design, wherein the first logical timing constraint point comprises a second delay parameter associated with the second block-level circuit design and a second clock source parameter specifying a second clock source associated with the second block-level circuit design;determine a second logical timing constraint point for the input port of the second block-level circuit design from the chip-level timing constraints of the chip-level circuit design, wherein the second logical timing constraint point comprises a first delay parameter associated with the first block-level circuit design and a first clock source parameter specifying a first clock source associated with the second block-level circuit design;independently perform a block-level timing analysis of the first block-level circuit design using the first logical timing constraint point;independently perform a block-level timing analysis of the second block-level circuit design using the second logical timing constraint point; andif timing is not met by a block, then modify a design of the block to generate a modified block to meet block level timing.