Iterative decoder systems and methods

摘要

Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR RAM, thus resulting in a less complex design and shorter processing times. In some embodiments, an intermediate memory may be used when passing information between the SOVA and LDPC of the iterative decoder. In some embodiments, the SOVA-required information may be continuously serialized from information received from the LDPC during each LDPC iteration. In some embodiments, the 1/(1+D2) precoder of the HR RLL encoder may be split into two serial, 1/(1+D) precoders. One 1/(1+D) precoder may be pulled outside of the HR RLL encoder and used in conjunction with the iterative decoder. A 1/(1+D) precoder may be used with the iterative decoder while maintaining the RLL constraints imposed upon the encoded information by the HR RLL encoder.

主权项

1. A method for generating encoded information, the method comprising:
receiving an input signal; generating a high rate run length limited (HR RLL) encoded signal with an HR RLL encoder; generating parity bits from the HR RLL encoded signal; interleaving the parity bits with the HR RLL encoded signal to generate a parity signal; and processing the parity signal with a precoder, wherein RLL constraints are imposed on the encoded information by a combined operation of the HR RLL encoder and the precoder.