Tracking scheme for memory

摘要

A memory has a tracking circuit for a read tracking operation. The memory includes a memory bit cell array, a tracking column, a tracking row, a sense amplifier row coupled to the memory bit cell array and the tracking row, and a sense amplifier enable logic. The memory further includes a tracking bit line coupled to the tracking column and the sense amplifier enable logic, and a tracking word line coupled to the tracking row and the sense amplifier enable logic. The tracking circuit is configured to track a column time delay along the tracking column before a row time delay along the tracking row.

主权项

1. A memory having a tracking circuit for a read tracking operation, comprising:
a memory bit cell array; a tracking column; a tracking row; a sense amplifier row coupled to the memory bit cell array and the tracking row; a sense amplifier enable logic; a tracking bit line coupled to the tracking column and the sense amplifier enable logic; a tracking word line coupled to the tracking row and the sense amplifier enable logic, wherein the tracking circuit is configured to track a column time delay along the tracking column before a row time delay along the tracking row, and the sense amplifier enable logic is configured to receive an output from the tracking column along the tracking bit line and to activate the tracking word line in response to the received output; and a latch clock generator coupled to the tracking bit line, the latch clock generator configured to supply a tracking clock signal, in the sense amplifier row, a sense amplifier in the sense amplifier row farthest from the sense amplifier enable logic being configured to generate a reset signal for the latch clock generator.