发明名称 |
Time-to-digital conversion circuit and time-to-digital converter including the same |
摘要 |
A time-to-digital conversion circuit for converting a time difference between two input signals to a 1-bit digital value, and adjusting the time difference between the two input signals to generate two output signals includes: a phase comparator configured to compare phases of the two input signals with each other to generate the digital value; a phase selector configured to output one of the two input signals which has a leading phase as a first signal, and the other of the two input signals which has a lagging phase as a second signal; and a delay unit configured to output the first signal with a delay, wherein the time-to-digital conversion circuit outputs the signal output from the delay unit and the second signal as the two output signals. |
申请公布号 |
US8976054(B2) |
申请公布日期 |
2015.03.10 |
申请号 |
US201313942478 |
申请日期 |
2013.07.15 |
申请人 |
Panasonic Intellectual Property Management Co., Ltd. |
发明人 |
Dosho Shiro;Takayama Masao;Miki Takuji |
分类号 |
H03M1/50;G04F10/00 |
主分类号 |
H03M1/50 |
代理机构 |
McDermott Will & Emery LLP |
代理人 |
McDermott Will & Emery LLP |
主权项 |
1. A time-to-digital conversion circuit for converting a time difference between two input signals to a 1-bit digital value, and adjusting the time difference between the two input signals to generate two output signals, the time-to-digital conversion circuit comprising:
a phase comparator configured to compare phases of the two input signals with each other to generate the digital value; a phase selector configured to output one of the two input signals which has a leading phase as a first signal, and the other of the two input signals which has a lagging phase as a second signal; and a delay unit configured to output the first signal with a delay, wherein the time-to-digital conversion circuit outputs the signal output from the delay unit and the second signal as the two output signals. |
地址 |
Osaka JP |