发明名称 |
Insert carrier and method for the simultaneous double-side material-removing processing of semiconductor wafers |
摘要 |
An insert carrier is configured to receive at least one semiconductor wafer for double-side processing of the wafer between two working disks of a lapping, grinding or polishing process. The insert carrier includes a core of a first material that has a first surface and a second surface, and at least one opening configured to receive a semiconductor wafer. A coating at least partially covers the first and second surfaces of the core. The coating includes a surface remote from the core that includes a structuring including elevations and depressions. A correlation length of the elevations and depressions is in a range of 0.5 mm to 25 mm and an aspect ratio of the structuring is in a range of 0.0004 to 0.4. |
申请公布号 |
US8974267(B2) |
申请公布日期 |
2015.03.10 |
申请号 |
US201113311575 |
申请日期 |
2011.12.06 |
申请人 |
Siltronic AG |
发明人 |
Pietsch Georg;Kerstan Michael |
分类号 |
B24B1/00;B24B37/28 |
主分类号 |
B24B1/00 |
代理机构 |
Leydig, Voit & Mayer, Ltd. |
代理人 |
Leydig, Voit & Mayer, Ltd. |
主权项 |
1. An insert carrier configured to receive at least one semiconductor wafer for double-side processing of the wafer between two working disks of a lapping, grinding or polishing process, the insert carrier comprising:
a core including a first material and having a first surface and a second surface; at least one opening configured to receive a semiconductor wafer; and a coating at least partially covering the first and second surfaces of the core, the coating including a surface remote from the core that includes a structuring including a multiplicity of elevations and depressions distributed in a pattern across the coating such that a correlation length of the elevations and depressions is in a range of 0.5 mm to 25 mm, and wherein an aspect ratio of the structuring is in a range of 0.0004 to 0.4. |
地址 |
Munich DE |