Electrostatic discharge blocking circuits

摘要

Techniques and architectures corresponding to electrostatic discharge blocking circuits are described.

主权项

1. A circuit arrangement for electrostatic discharge protection comprising:
a MOS buffer transistor configured to receive an input signal from a first functional circuit block at a gate of the MOS buffer transistor and to provide at least a portion of an output signal to a second functional circuit block; and a MOS blocking transistor coupled to the MOS buffer transistor, wherein a gate of the MOS blocking transistor is coupled to a supply voltage, and wherein a body terminal of the MOS blocking transistor and a body terminal of the MOS buffer transistor are coupled to another blocking transistor.