Densely packed standard cells for integrated circuit products, and methods of making same

摘要

One method disclosed herein includes forming first and second transistor devices in and above adjacent active regions that are separated by an isolation region, wherein the transistors comprise a source/drain region and a shared gate structure, forming a continuous conductive line that spans across the isolation region and contacts the source/drain regions of the transistors and etching the continuous conductive line to form separated first and second unitary conductive source/drain contact structures that contact the source/drain regions of the first and second transistors, respectively. A device disclosed herein includes a gate structure, source/drain regions, first and second unitary conductive source/drain contact structures, each of which contacts one of the source/drain regions, and first and second conductive vias that contact the first and second unitary conductive source/drain contact structures, respectively.

主权项

1. A method, comprising:
forming first and second transistor devices in and above adjacent first and second active regions that are separated by an isolation region formed in a semiconductor substrate, said first and second transistors comprising at least one source/drain region and a shared gate structure: forming a continuous conductive line that spans across said isolation region, wherein said continuous conductive line contacts said at least one source/drain region of each of said first and second transistors; and performing an etching process through a patterned mask layer on said at least one continuous conductive line to form separated first and second unitary conductive source/drain contact structures, wherein said first unitary conductive source/drain contact structure contacts only said at least one source/drain region of said first transistor and said second unitary conductive source/drain contact structure contacts only said at least one source/drain region of said second transistor.