发明名称 Device including two power semiconductor chips and manufacturing thereof
摘要 A device includes a first power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The device further includes a second power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The first and second power semiconductor chips are arranged one above another, and the first face of the first power semiconductor chip faces in the direction of the first face of the second power semiconductor chip. In addition, the first power semiconductor chip is located laterally at least partially outside of the outline of the second power semiconductor chip.
申请公布号 US8975711(B2) 申请公布日期 2015.03.10
申请号 US201113314438 申请日期 2011.12.08
申请人 Infineon Technologies AG 发明人 Otremba Ralf;Hoeglauer Josef;Mahler Joachim;Lodermeyer Johannes
分类号 H01L29/72;H01L23/00;H01L23/492;H01L21/48;H01L23/538;H01L21/56;H01L25/07;H01L25/00;H01L23/31 主分类号 H01L29/72
代理机构 Slater & Matsil, L.L.P. 代理人 Slater & Matsil, L.L.P.
主权项 1. A device, comprising: a first power semiconductor chip having a first face and a second face opposite the first face, wherein a first contact pad and a second contact pad are arranged on the first face and a third contact pad is arranged on the second face, and wherein a first metal layer is attached to the second face of the first power semiconductor chip; and a second power semiconductor chip having a first face and a second face opposite the first face, wherein a first contact pad and a second contact pad are arranged on the first face and a third contact pad is arranged on the second face, wherein the first and second power semiconductor chips are arranged such that the first face of the first power semiconductor chip faces in a first direction and the first face of the second power semiconductor chip faces in a second direction opposite to the first direction, wherein the first power semiconductor chip is located laterally at least partially outside of an outline of the second power semiconductor chip, and wherein the first metal layer electrically couples the third contact pad of the first power semiconductor chip to the first contact pad of the second power semiconductor chip.
地址 Neubiberg DE