发明名称 |
CLOCK SIGNAL GENERATION CIRCUIT, DISPLAY PANEL MODULE, IMAGE SENSOR APPARATUS, AND ELECTRONIC APPARATUS |
摘要 |
A clock signal generation circuit of a delay locked loop type includes a delay line configured to delay a first clock signal to generate a second clock signal; a delay amount controller configured to change the amount of delay in the delay line in such a manner that a phase of the second clock signal is in synchronization with a phase of the first clock signal; a pseudo-lock detection section configured to detect a pseudo-locked state of the first clock signal and the second clock signal; and a pseudo-locked state release section configured to change the amount of delay in the delay line in a case that the pseudo-locked state is detected. |
申请公布号 |
KR101499630(B1) |
申请公布日期 |
2015.03.06 |
申请号 |
KR20080099542 |
申请日期 |
2008.10.10 |
申请人 |
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发明人 |
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分类号 |
G06F1/06;G09G3/20;G09G3/36;H03K5/00;H03L7/08;H03L7/081;H03L7/095;H04N5/04;H04N5/335;H04N5/357 |
主分类号 |
G06F1/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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