OSCILLATOR CIRCUIT, A SEMICONDUCTOR DEVICE AND AN APPARATUS

摘要

An oscillator circuit for providing an output clock signal is described. The oscillator circuit comprising a voltage reference, a first current source, first capacitor, first capacitor switch, second current source, second capacitor, second capacitor switch, first comparator, second comparator and flip-flop. The first comparator comprises a first chopper-stabilized comparator switchable between a compare phase and a zeroing phase in dependence on the output clock signal and arranged to operate in the compare phase in a first half-phase of the output clock signal to provide a first comparator output from comparing the first capacitor voltage to the reference voltage and in the zeroing phase in the second half-phase. The second comparator comprises a second chopper-stabilized comparator switchable between a respective compare phase and a respective zeroing phase in dependence on the output clock signal and arranged to operate in its compare phase in the second half-phase to obtain a second comparator output from comparing the second capacitor voltage to the reference voltage and in its zeroing phase in the first half-phase.

主权项

1. An oscillator circuit for providing an output clock signal having an output frequency, the oscillator circuit comprising a voltage reference, a first current source, a first capacitor, a first capacitor switch, a second current source, a second capacitor, a second capacitor switch, a first comparator, a second comparator and a flip-flop,
the voltage reference arranged to carry a reference voltage, the first capacitor arranged to, by operation of the first capacitor switch, be chargeable by the first current source to a first capacitor voltage on a first capacitor node in a first half-phase of the output clock and to be dischargeable in a second half-phase of the output clock; the second capacitor arranged to, by operation of the second capacitor switch, be chargeable by the second current source to a second capacitor voltage on a second capacitor node in the second half-phase of the output clock and to be dischargeable in a first half-phase of the output clock; the first comparator comprising a first chopper-stabilized comparator switchable between a compare phase and a zeroing phase in dependence on the output clock signal and arranged to operate in the compare phase in the first half-phase to provide a first comparator output from comparing the first capacitor voltage to the reference voltage and arranged to operate in the zeroing phase in the second half-phase; the second comparator comprising a second chopper-stabilized comparator switchable between a respective compare phase and a respective zeroing phase in dependence on the output clock signal and arranged to operate in its compare phase in the second half-phase to obtain a second comparator output from comparing the second capacitor voltage to the reference voltage and arranged to operate in its zeroing phase in the first half-phase phase; the flip-flop being connected to the first comparator and the second comparator to receive the first comparator output and the second comparator output for generating the output clock signal and connected to the first comparator and the second comparator for providing the output clock signal to the first comparator and the second comparator.