Reducing Latency OF Unified Memory Transactions

摘要

In an embodiment, an apparatus includes a consuming logic to request and process data including a critical data portion and a second data portion, the data stored in a memory coupled to a processor interposed between the apparatus and the memory. In addition, the apparatus includes a protocol stack logic coupled to the consuming logic to issue a read request to the memory via the processor to request the data and to receive a plurality of completions responsive to the read request. In an embodiment, the protocol stack logic includes a completion handling logic to send data of a first of the completions to the consuming logic before protocol stack processing is completed on the completions. Other embodiments are described and claimed.

主权项

1. An apparatus comprising:
a receiver to receive a memory request, the memory request to request a block of data to begin at a particular address, the particular address to be unaligned to an alignment boundary of a memory line of a memory, the receiver to send at least a first read request to the memory to request the data block; a generator to receive the data block, generate a first completion packet to include a first portion of the data block, and generate a second completion packet to include a second portion of the data block; and a transmitter to send the first completion packet before the second completion packet.