| 发明名称 |
REDUNDANCY IN STACKED MEMORY STRUCTURE |
| 摘要 |
A circuit includes stacked memory arrays and a control circuit. The stacked memory arrays includes a first layer and a second layer. The control circuit is configured to receive a first address in the first layer; cause the second layer to be enabled for accessing; and provide a second row address for accessing the second layer. |
| 申请公布号 |
US2015063039(A1) |
申请公布日期 |
2015.03.05 |
| 申请号 |
US201314014107 |
申请日期 |
2013.08.29 |
| 申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. |
发明人 |
CHEN CHIEN-YUAN;HUANG CHIEN-YU;CHEN YI-TZU;SHIEH HAU-TAI |
| 分类号 |
G11C29/04 |
主分类号 |
G11C29/04 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method, comprising:
receiving a first address in a first layer of stacked memory arrays; causing a second layer of stacked memory arrays to be enabled for accessing; and providing a second row address for accessing the second layer. |
| 地址 |
Hsinchu TW |
