CONSTANT VOLTAGE CONSTANT CURRENT CONTROL CIRCUITS AND METHODS WITH IMPROVED LOAD REGULATION

摘要

The present invention discloses CVCC circuits and methods with improved load regulation for an SMPS. In one embodiment, the CVCC can include: a voltage feedback circuit to generate an output voltage feedback signal; a current feedback circuit to generate an output current feedback signal; a control signal generating circuit that receives the output voltage feedback signal and the output current feedback signal, and generates a constant voltage/constant current control signal; a first enable signal generating circuit that compares a first reference voltage and the constant voltage/constant current control signal to generate a first enable signal; and a PWM controller that generates a PWM control signal based on the constant voltage/constant current control signal to control a main switch of the flyback SMPS.

主权项

1. A constant voltage/constant current (CVCC) control circuit for regulation of a load of a flyback switch mode power supply (SMPS), the CVCC control circuit comprising:
a) a voltage feedback circuit configured to generate an output voltage feedback signal; b) a current feedback circuit configured to generate an output current feedback signal; c) a control signal generating circuit configured to receive said output voltage feedback signal and said output current feedback signal, to control whether said flyback SMPS operates in a constant voltage mode or a constant current mode based on a first control signal and an error signal, and to generate a CVCC control signal; d) a first enable signal generating circuit configured to compare a first reference voltage and said CVCC control signal to generate a first enable signal; and e) a pulse-width modulation (PWM) controller configured to generate a PWM control signal based on said CVCC control signal to control a main switch of said flyback SMPS, wherein said PWM control signal is configured to turn on said main switch when said first enable signal is inactive, and wherein said main switch remains off when said first enable signal is active.