| 摘要 |
A design method of a repeater chip is provided, the repeater chip designed by using the method can implement interconnection among nodes, and implement packet sequence receiving, classifying, storing, forwarding, sorting, and transmitting functions of the repeater chip, thereby implementing effective extension of a high-speed transmission link among the nodes, so as to reduce hardware design difficulties and design risks. The structure of the repeater chip is formed by: an interface detecting unit, a sequence storing unit, a sequence forwarding unit, a sequence determining unit, and a sequence sorting unit. |
| 主权项 |
1. A design method of a repeater chip, comprising:
the repeater chip is used to implement interconnection among nodes, and implement packet sequence receiving, classifying, storing, forwarding, sorting, and transmitting functions of the repeater chip, thereby implementing effective extension of a high-speed transmission link among the nodes, so as to reduce hardware design difficulties and design risks, and a structure of the repeater chip comprises: (1) an interface detecting unit, (2) a sequence storing unit, (3) a sequence forwarding unit, (4) a sequence determining unit, and (5) a sequence sorting unit, wherein: for the interface detecting unit (1), according to features of a transmission link of a repeater chip application system, a clock detecting unit and a data detecting unit are designed in the interface detecting unit (1); in a power-on initial period of the system, the transmission link automatically detect connectivity of a link between an interconnection component and the repeater chip, and if a connectivity problem exists, a redundancy link is used to replace the failed link; for the sequence storing unit (2), the sequence storing unit (2) is implemented by using an FIFO according to function features of the repeater chip, that is, to store packets received by a PORT-L or PORT-R port, and in order to improve the performance of the repeater chip, multiple groups of FIFO storing units are implemented respectively according to different types of the received packets, so as to store various types of packets, wherein the packet types are distinguished by using the sequence determining unit (4); for the sequence forwarding unit (3), the received packet sequence, after being stored by the sequence storing unit, is forwarded by the packet sequence forwarding unit (3), wherein different types of packets are forwarded by using different channels, thereby improving execution efficiency; for the sequence determining unit (4), to improve the performance of the repeater chip, the sequence determining unit (4) is designed to distinguish effective packets from ineffective packets, and classify the effective packets according to respective types, thereby improving packet sequence processing efficiency of the repeater chip; and for the sequence sorting unit (5), the different types of packets, after being forwarded, are sorted by the sequence sorting unit (5) according to an order of packet transmission and a quantity requirement of the same packets, and then are sent through the PORT-R or PORT-L and transmitted to the other node. |
