DEVELOPMENT AND DEBUG ENVIRONMENT IN A CONSTRAINED RANDOM VERIFICATION

摘要

A design verification workstation contains both debug and constraint solver capabilities during simulation of a design under test. The design verification workstation is configured to allow the user to debug constraints, stop the constraint solver, navigate problems and variables, and make modifications on-the fly during the simulation to constraint information. Additionally, in some embodiments, the design verification workstation may allow a user to use a constraint solver to experiment if the modifications will lead to desired test stimulus. Since this debug process happens during simulation, users do not need to recompile the test case. Additionally, once a user is satisfied with the modifications made to the simulation, the modification could be saved for future usage.

主权项

1. A system to debug constraints in a design simulation, comprising:
a processor configured to execute modules; and a memory storing the modules, the modules comprising:
a design verification environment configured to:
pause the design simulation and execute a constraint solver in response to reaching a breakpoint in the design simulation, the design simulation including constraint information that includes a plurality of constraints,present constraint static information that describes an organization of a portion of the plurality of constraints,present constraint dynamic information that describes an activity level of the portion of the plurality of constraints,receive a modification of the constraint information,execute a call to solve the portion of the plurality of constraints using the modified constraint information and the constraint solver to create one or more results, andresume the design simulation using the modified constraint information without re-starting the design simulation.