| 发明名称 |
MULTI-CORE HARDWARE SEMAPHORE |
| 摘要 |
A microprocessor includes a plurality of processing cores, a resource shared by the plurality of processing cores, and a hardware semaphore readable and writeable by each of the plurality of processing cores within a non-architectural address space. Each of the plurality of processing cores is configured to write to the hardware semaphore to request ownership of the shared resource and to read from the hardware semaphore to determine whether or not the ownership was obtained. Each of the plurality of processing cores is configured to write to the hardware semaphore to relinquish ownership of the shared resource. |
| 申请公布号 |
US2015067250(A1) |
申请公布日期 |
2015.03.05 |
| 申请号 |
US201414281585 |
申请日期 |
2014.05.19 |
| 申请人 |
VIA TECHNOLOGIES, INC. |
发明人 |
Henry G. Glenn;Parks Terry |
| 分类号 |
G06F12/08 |
主分类号 |
G06F12/08 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A microprocessor, comprising:
a plurality of processing cores; a resource, shared by the plurality of processing cores; and a hardware semaphore, readable and writeable by each of the plurality of processing cores within a non-architectural address space; wherein each of the plurality of processing cores is configured to write to the hardware semaphore to request ownership of the shared resource and to read from the hardware semaphore to determine whether or not the ownership was obtained; and wherein each of the plurality of processing cores is configured to write to the hardware semaphore to relinquish ownership of the shared resource. |
| 地址 |
New Taipei City TW |
