发明名称 MEMORY MANAGEMENT DEVICE
摘要 <p>PROBLEM TO BE SOLVED: To efficiently allocate a normal block and a degenerate block to writing data in an MLC NAND flash memory.SOLUTION: A NAND flash memory chip 200 includes a normal block whose number of bits per one cell is k bit (k≥2), and a degenerate block whose number of bits per one cell is j bit (j>k). A command interface section 101 inputs writing data to the NAND flash memory chip 200 by a plurality of input rates. An allocation block controller 106 determines the number of the normal blocks and the number of the degenerate blocks used for writing the writing data on the basis of the input rate of the writing data.</p>
申请公布号 JP2015043183(A) 申请公布日期 2015.03.05
申请号 JP20130175018 申请日期 2013.08.26
申请人 MITSUBISHI ELECTRIC CORP 发明人 KUROSAWA HISAYOSHI
分类号 G06F12/16 主分类号 G06F12/16
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