发明名称 Low-power data acquisition system and sensor interface
摘要 A sensor interface includes on-chip relaxation oscillator circuit and a PLL that operate cooperatively to generate a highly accurate clock signal on-chip using low-power components. A photodiode generates a current signal based on an optical signal that is representative of a sensor signal. An ADC that operates based on the highly accurate clock signal generates a digital signal based on the current signal generated by the photodiode, and a processor processed the digital signal to estimate sensor data within the sensor signal. Examples of characteristics that may be sensed can include environmental characteristics (e.g., temperature, humidity, barometric pressure, etc.) and/or biomedical characteristics (e.g., body temperature, heart rate, respiratory rate, blood pressure, etc.). In desired, an amplifier processes the photodiode-provided current signal before it is provided to the ADC. Also, one or more CDACs that generate feedback currents may be used to reduce noise sensitivity of the sensor interface.
申请公布号 US2015066438(A1) 申请公布日期 2015.03.05
申请号 US201414473635 申请日期 2014.08.29
申请人 BROADCOM CORPORATION 发明人 Brooks Todd Lee;Jiang Xicheng;Mehr Iuri;Stoops David Joseph;Jayakumar Vinod;Kim Min Gyu;Zheng Hui;Ku I-Ning;Chandrasekhar Vinay;Cheung Yee Ling
分类号 H03B5/04;G01R19/00;G01K1/00;G01L7/00;A61B5/021;H05B33/08;A61B5/01;A61B5/024;A61B5/08;G01J1/00;G01N33/00 主分类号 H03B5/04
代理机构 代理人
主权项 1. A sensor interface comprising: an on-chip relaxation oscillator circuit configured to generate a first clock signal; a digital phase locked loop (PLL) configured to generate a second clock signal based on the first clock signal, wherein the second clock signal is synchronized to the first clock signal; a photodiode configured to generate a first current signal based on an optical signal, wherein the optical signal is representative of a sensor signal; an amplifier configured to generate a second current signal based on the first current signal and a feedback current signal; an analog to digital converter (ADC) configured to operate based on the second clock signal and to generate a digital signal based on the second current signal; a current digital to analog converter (CDAC) configured to operate based on the second clock signal and to generate an updated feedback current signal based on the digital signal, wherein the updated feedback current signal reduces noise sensitivity of the amplifier; and a processor configured to process the digital signal to estimate sensor data within the sensor signal.
地址 Irvine CA US