发明名称 STACKED SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME
摘要 A stacked semiconductor package includes a first semiconductor chip having a first surface and a second surface which faces away from the first surface and including first bonding pads which are formed on the first surface and first through electrodes which pass through the first surface and the second surface; a second semiconductor chip stacked over the second surface of the first semiconductor chip, and including second bonding pads which are formed on a third surface facing the first semiconductor chip and second through electrodes which pass through the third surface and a fourth surface facing away from the third surface and are electrically connected with the first through electrodes; and a molding part formed to substantially cover the stacked first and second semiconductor chips and having openings which expose one end of the first through electrodes disposed on the first surface of the first semiconductor chip.
申请公布号 US2015064843(A1) 申请公布日期 2015.03.05
申请号 US201414536002 申请日期 2014.11.07
申请人 SK hynix Inc. 发明人 CHOI Hyeong Seok
分类号 H01L25/00;H01L21/56;H01L21/768;H01L21/78;H01L23/00 主分类号 H01L25/00
代理机构 代理人
主权项 1. A method for manufacturing a stacked semiconductor package, comprising: forming first through electrodes in a first wafer which is formed with a plurality of first semiconductor chips each having first bonding pads, to pass through first surfaces of the first semiconductor chips on which the first bonding pads are disposed; forming a first molding part on the first wafer to cover the first surfaces of the first semiconductor chips; exposing the first through electrodes on second surfaces of the first semiconductor chips which face away from the first surfaces; stacking a second wafer including a plurality of second semiconductor chips each having second bonding pads and formed with second through electrodes to a depth that passes through third surfaces on which the second bonding pads are disposed and does not reach fourth surfaces which face away from the third surfaces, over the first wafer such that the second through electrodes are electrically connected with the first through electrodes; exposing the second through electrodes on the fourth surfaces of the second semiconductor chips; individualizing the first and second semiconductor chips; forming a second molding part on the first molding part including the stacked first and second semiconductor chips; and partially removing the first molding part to expose one end of the first through electrodes.
地址 Icheon-si KR