| 发明名称 |
SEMICONDUCTOR MEMORY DEVICE |
| 摘要 |
A semiconductor memory device includes: banks each including a memory cell array; word lines connected to rows of each of the banks; an address latch circuit configured to latch a full address for specifying one of the word lines, the full address including a first address and a second address; and a control circuit configured to ignore a reset operation for the first address as a target of a set operation, and overwrite the first address in accordance with the set operation when receiving a first command for specifying a reset operation for a bank and a set operation for the first address. |
| 申请公布号 |
US2015063015(A1) |
申请公布日期 |
2015.03.05 |
| 申请号 |
US201414201618 |
申请日期 |
2014.03.07 |
| 申请人 |
SHIMIZU Naoki |
发明人 |
SHIMIZU Naoki |
| 分类号 |
G11C11/16 |
主分类号 |
G11C11/16 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A semiconductor memory device comprising:
banks each including a memory cell array; word lines connected to rows of each of the banks; an address latch circuit which latches a full address for specifying one of the word lines, the full address including a first address and a second address; and a control circuit which ignores a reset operation for the first address as a target of a set operation, and overwrites the first address in accordance with the set operation when receiving a first command for specifying a reset operation for a bank and a set operation for the first address. |
| 地址 |
Seoul KR |
