| 发明名称 |
SEMICONDUCTOR MEMORY DEVICE |
| 摘要 |
A semiconductor memory device is capable of executing a first mode having a first latency and a second mode having a second latency longer than the first latency. The semiconductor memory device includes: a pad unit configured to receive an address and a command from an outside; a first delay circuit configured to delay the address by a time corresponding to the first latency; a second delay circuit including shift registers connected in series and configured to delay the address by a time corresponding to a difference between the first latency and the second latency; and a controller configured to use the first delay circuit and the second delay circuit when executing the second mode. |
| 申请公布号 |
US2015063017(A1) |
申请公布日期 |
2015.03.05 |
| 申请号 |
US201414201686 |
申请日期 |
2014.03.07 |
| 申请人 |
SHIMIZU Naoki;BAE Ji Hyae |
发明人 |
SHIMIZU Naoki;BAE Ji Hyae |
| 分类号 |
G11C11/16 |
主分类号 |
G11C11/16 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A semiconductor memory device capable of executing a first mode having a first latency and a second mode having a second latency longer than the first latency, comprising:
a pad unit which receives an address and a command from an outside; a first delay circuit which delays the address by a time corresponding to the first latency; a second delay circuit which includes shift registers connected in series and delays the address by a time corresponding to a difference between the first latency and the second latency; and a controller which uses the first delay circuit and the second delay circuit when executing the second mode. |
| 地址 |
Seoul KR |
