发明名称 Three-Dimensional Chip Stack and Method of Forming the Same
摘要 A three-dimensional chip stack includes a first chip bonded to a second chip to form a bonded interconnection therebetween. The bonded interconnection includes a first conductive pillar overlying a first substrate of the first chip, a second conductive pillar overlying a second substrate of the second chip, and a joint structure between the first conductive pillar and the second conductive pillar. The joint structure includes a first IMC region adjacent to the first conductive pillar, a second IMC region adjacent to the second conductive pillar, and a metallization layer between the first IMC region and the second IMC region.
申请公布号 US2015061118(A1) 申请公布日期 2015.03.05
申请号 US201314016966 申请日期 2013.09.03
申请人 Taiwan Semiconductor Manufacturing Company, Ltd. 发明人 Chen Wei-Ming;Hsieh Cheng-Hsien;Huang Sung-Hui;Hsu Kuo-Ching
分类号 H01L23/00;B23K1/00;H01L25/065 主分类号 H01L23/00
代理机构 代理人
主权项 1. A three-dimensional chip stack, comprising: a first chip comprising a first substrate; and a second chip comprising a second substrate; wherein the first chip is bonded to the second chip to form a bonded interconnection between the first substrate and the second substrate, wherein the bonded interconnection comprises a first conductive pillar overlying the first substrate, a second conductive pillar overlying the second substrate, and a joint structure between the first conductive pillar and the second conductive pillar; and wherein the joint structure comprises a first intermetallic compound (IMC) region adjacent to the first conductive pillar, a second IMC region adjacent to the second conductive pillar, and a metallization layer between the first IMC region and the second IMC region.
地址 Hsin-Chu TW