| 摘要 |
<p>A semiconductor device comprises a memory array which comprises memory cells; page buffers which perform the read operations of the memory cells; cache latch circuits which latch the data read by the page buffers and output the data to data lines in response to a column selection signal inputted through a column selection line; a column selecting device which outputs the column selection signal to the column selection line in response to a column address; and a sense amplifier which senses the voltage of the data lines and outputs the data. The column selecting device and the sense amplifiers are arranged to inversely compare the length of the column selection line with the length of the data lines which are connected to each cache latch circuit. The present invention improves the input/output speed of the data.</p> |
