| 摘要 |
<p>A data processing apparatus for processing a stream of vector instructions for performing operations on vectors, said vectors each comprising a plurality of data elements is disclosed. The data processing apparatus comprises: a register bank having a plurality of registers for storing the vectors being processed; a pipelined processor for processing the stream of vector instructions; the pipelined processor comprising circuitry configured to detect data dependencies for the vectors processed by the stream of vector instructions and stored in the plurality of registers and to determine constraints on timing of execution for the vector instructions such that no register data hazards arise, said register data hazards arising where two accesses to a same register, at least one of said accesses being a write, occur in an order different to an order of said instruction stream such that an access occurring later in said instruction stream starts before an access occurring earlier in said instruction stream has completed. The pipelined processor comprises data element hazard determination circuitry configured to determine for at least some of the data elements within vectors where data dependencies have been identified, whether the data dependencies identified for the vectors exist for each of the at least some of the data elements, and if not to relax the determined constraints on timing of execution for an instruction processing the data element.</p> |
