| 摘要 |
<p>A decoding apparatus for low density parity check codes includes a variable-to-check message generator 11 and a check-to-variable message generator 12. The variable-to-check message generator includes a variable-to-check processing unit block 32, provided with an adder 41, and which is arranged between registers 31 corresponding to locations of '1's in a check matrix. The check-to-variable message generator 12 includes a check-to-variable processing unit block 62, provided with a comparator, between registers 61 corresponding to locations of '1's in the check matrix. The decoding apparatus for low density parity check codes is simple in configuration and is able to perform high speed processing without using RAMs without the necessity of performing complex control operations.</p> |
