| 摘要 |
<p>An arithmetic processing device includes: a first instruction execution unit configured to include plural staging latches and execute a first instruction by a pipeline operation requiring only a single clock for transition of data between first plural, staging latches including a staging latch at a final stage from among the plural staging latches, and a multi-cycle operation requiring plural clocks for transition of data between second plural staging latches positioning at a previous stage side than the first plural staging latches from among the plural staging latches; a second instruction, execution, unit configured to execute a second instruction; and an instruction control unit configured to input the first instruction and the second instruction, issue the first instruction to the first instruction execution unit and issue the second instruction to the second instruction execution unit such that the execution of the first instruction and the second instruction are partly overlapped.</p> |
