发明名称 受信回路及び電子装置
摘要 <p><P>PROBLEM TO BE SOLVED: To reduce the area and power consumption of a reception circuit in an electronic apparatus. <P>SOLUTION: The reception circuit includes: a plurality of sampling circuits (SWs) for sampling received data at different timings; a plurality of hold circuits (C) for holding the respective data sampled by the plurality of sampling circuits; parameter calculation circuits (70, 72, 74) for calculating parameters for determining the degree of equalization and interpolation of the input signal in accordance with outputs from the plurality of hold circuits; a weighting circuit (76) for weighting the outputs of the plurality of hold circuits according to the parameters calculated by the parameter calculation circuits; and an output circuit (N3) for combining and outputting the output data from the hold circuits weighted by the weighting circuit. <P>COPYRIGHT: (C)2012,JPO&INPIT</p>
申请公布号 JP5678672(B2) 申请公布日期 2015.03.04
申请号 JP20110001883 申请日期 2011.01.07
申请人 发明人
分类号 H03M1/12 主分类号 H03M1/12
代理机构 代理人
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