Shift register and gate driver with compensation control

摘要

A shift register including a plurality of multi-stage shift register circuits is provided. The mth stage shift register circuit includes a node, a shift register unit and a control circuit. A first control signal, enabled in an mth period, is defined on the node. The shift register unit is controlled by an (m−1)th stage output signal provided by an (m−1)th stage shift register circuit and a clock signal for providing the enabled mth stage output signal in the mth period, and controlled by an (m+1)th stage second control signal provided by an (m+1)th stage shift register circuit for providing a disenabled mth stage output signal in the (m+1)th period. The control circuit, controlled by the clock signal, provides and outputs an mth stage second control signal to the (m−1)th stage shift register circuit according to the mth stage first control signal, wherein m is a natural number greater than 1.

主权项

1. A shift register comprising a plurality of multi-stage shift register circuits respectively used for outputting a plurality of shift output signals, wherein an mth stage shift register circuit of the multi-stage shift register circuits comprises:
an mth stage first node, wherein an mth stage first control signal enabled in an mth period is defined on the mth stage first node; an mth stage shift register unit controlled by a first clock signal and an (m−1)th stage output signal enabled in an (m−1)th period and provided by an (m−1)th stage shift register circuit, for providing an enabled mth stage output signal in the mth period, wherein the mth stage shift register unit further is controlled by an (m+1)th stage second control signal provided by an (m+1)th stage shift register circuit for providing the disenabled mth stage output signal in an (m+1)th period; and an mth stage control circuit controlled by the first clock signal for providing and outputting an mth stage second control signal to the (m−1)th stage shift register circuit according to the mth stage first control signal; wherein m is a natural number greater than 1, the mth stage output signal is applied to an output line to drive a display panel, the output line is connected to the display panel and the (m+1)th stage shift register circuit, but is not connected to the previous stage shift register circuit, so that the mth stage shift register circuit does not provide the mth stage output signal to the previous stage shift register circuit; wherein an output load of the mth stage shift register circuit does not include a load of the (m−1)th stage shift register circuit; and wherein the mth stage control circuit comprises:
a second node, wherein the mth stage second control signal is defined on the second node;a first transistor, wherein a first input end is coupled to the mth stage first node, a second input end is coupled to the second node, and the control end receives the first clock signal; anda second transistor, wherein the first input end is coupled to the second node, the second input end receives a reference voltage signal, and the control end receives a second clock signal.