发明名称 System, method, and device to distribute accurate synchronization timestamps in an expandable and timing critical system
摘要 Techniques are described to provide a device and network of devices that collect distributed coordinated timestamps from distributed time counters in a multi-module or multi-integrated circuit system. The interconnect between the modules can be a single-wire or a two-wire interconnect. The modules communicatively coupled to the interconnect can use a collision-avoidance protocol for triggering the broadcasting of timestamps among the modules as well for allowing all modules to transmit their timestamps. Timestamps from multiple clocks can be transmitted by all modules and then collected and compared to produce correction factors to clock signals of each module to potentially achieve distributed clock synchronization in multiple independent modules or integrated circuits.
申请公布号 US8971470(B2) 申请公布日期 2015.03.03
申请号 US201113035623 申请日期 2011.02.25
申请人 Intel Corporation 发明人 Loukianov Dmitrii
分类号 H04L7/00;H04J3/06;G06F1/14 主分类号 H04L7/00
代理机构 International IP Law Group, P.L.L.C. 代理人 International IP Law Group, P.L.L.C.
主权项 1. A device comprising: an interface to an interconnect system, wherein when the interface is communicatively coupled to the interconnect system, the interface is to receive initiation of a time stamping event from the interconnect system; a time base comprising a clock and a time counter which is to increment or decrement its count each period of the clock; a time stamp generator to capture a count of the time base associated with the device, the time stamp generator to use the interface to transmit a time stamp event indicator to the interconnect system and also to transmit a device identifier to the interconnect system, wherein the interface is to transmit signals to simultaneously initiate the time stamping event in one or more other devices and to trigger transmission by the one or more other devices of device identifiers and timestamps to the interconnect system; and collision avoidance logic to determine whether the device is permitted to transmit its time stamp using the interconnect system, wherein the time stamp generator is to wait for a period of time and transmit the device identifier to the interconnect system again in response to the device not being permitted to transmits its time stamp, and wherein the interface comprises a bidirectional optical interconnect system and communication of bits occurs by modulating optical radiation and wherein collision avoidance logic is to detect collisions by monitoring optical signal intensity or phase to determine if a signal different from that transmitted by the interface is communicated by the interconnect system.
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