Detection of skip mode

摘要

A method to quickly determine whether a macroblock in H.264 or other similar standards should be encoded in skip mode in a SIMD processor environment is provided. The method exploits the fact that the processor provides enough register space to store N=4 4×4 set of 8 bits data. By performing 4 consecutive reads of 16 linear aligned values into 16 SIMD register variables each capable of storing 16 values, the entire data set for operating can be stored within the processors SIMD register variables and can be operated upon, without any memory related latency.

主权项

1. A method of video coding implemented in a processor device for preparing to determine whether 4×4 pixel blocks within a macroblock of transformed residual pixel values should be indicated as skipped according to a coding standard, where the pixel position values of the macroblock are denoted as xij, where i is the vertical pixel position within the macroblock and j is the horizontal pixel position of the macroblock, comprising the steps of:
I. loading current values of the macroblock of the positions one of: xi0 to xi3 into a first Single Instruction, Multiple Data (SIMD) vector, xi0 to xi3 and x(i+4)0 to X(i+4)3 into the first SIMD vector, and xi0 to xi3 and X(i+4)0 to x(i+4)3 and X(i+8)0 to X(i+8)3 and X(i+12)0 to X(i+12)3 into the first SIMD vector, and converting bytes of the first SIMD vector from unsigned to signed; II. loading predicted values of the macroblock of the positions one of: xi0 to xi3 into a second SIMD vector, xi0 to xi3 and x(i+4)0 to x(i+4)3 into the second SIMD vector, and xi0 to xi3 and x(i+4)0 to x(i+4)3 and x(i+8)0 to x(i+8)3 and X(i+12)0 to x(i+12)3 into the second SIMD vector, and converting bytes of the second SIMD vector from unsigned to signed; III. subtracting values of the first SIMD vector and the values of corresponding positions of the second SIMD vector and performing a 8-bit saturation of the resulting values and loading the resulting values into a third SIMD vector; IV. transforming the third SIMD vector horizontally with 8-bit saturation arithmetic and loading the result into a fourth SIMD vector; V. transposing the fourth SIMD vector; and VI. transforming the fourth transposed SIMD vector vertically with 8-bit saturation arithmetic and loading the result into a fifth SIMD vector.