Layout correcting method, recording medium and design layout correcting apparatus

摘要

In a design layout correcting method of an embodiment, a design layout of a circuit pattern is divided to a first mask pattern and a second mask pattern. The mask pattern of the pattern defect area of the first or second mask pattern is set as the correcting target pattern. A correcting target region and a verifying region are set within the first or second mask pattern. The correcting target pattern is corrected within the correcting target region, and the first and second mask patterns are verified within the verifying region.

主权项

1. A design layout correcting method implemented by a computer, the method comprising:
dividing a design layout of a circuit pattern formed in one layer into at least a first mask pattern and a second mask pattern; setting a design pattern corresponding to a pattern defect area of the first mask pattern or the second mask pattern as a correcting target pattern when correcting the first mask pattern or the second mask pattern; setting a correcting target region corresponding to an arrangement position of the correcting target pattern within the first mask pattern or the second mask pattern; setting a verifying region configured to perform verification of the correcting target region within the first mask pattern or the second mask pattern; correcting the correcting target pattern within the correcting target region; and verifying whether or not the first and second mask patterns are a desired design layout within the verifying region.