发明名称 |
Look-up table circuit |
摘要 |
One embodiment provides a look-up table circuit, including: 2i memories, a half of which constituting a first memory group, the other half of which constituting a second memory group; first to i-th input terminals to which first to i-th input signals are input, respectively; a first output terminal; a switch group that selectively connects one of the memories to the first output terminal according to the first to i-th input signals; a first power-off switch that shuts off power supply to the first memory group in response to one of the first to i-th input signals; and a second power-off switch that shuts off power supply to the second memory group in response to the one of the first to i-th input signals. |
申请公布号 |
US8970249(B2) |
申请公布日期 |
2015.03.03 |
申请号 |
US201213606041 |
申请日期 |
2012.09.07 |
申请人 |
Kabushiki Kaisha Toshiba |
发明人 |
Oda Masato;Yasuda Shinichi |
分类号 |
H03K19/173 |
主分类号 |
H03K19/173 |
代理机构 |
Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P. |
代理人 |
Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P. |
主权项 |
1. A look-up table circuit, comprising:
2i memories, a half of which constituting a first memory group, the other half of which constituting a second memory group; first to i-th input terminals to which first to i-th input signals are input, respectively; a first output terminal; a switch group that selectively connects one of the memories to the first output terminal according to the first to i-th input signals; a first power-off switch that shuts off power supply to the first memory group in response to one of the first to i-th input signals; and a second power-off switch that shuts off power supply to the second memory group in response to the one of the first to i-th input signals. |
地址 |
Tokyo JP |