发明名称 Transistor-based apparatuses, systems and methods
摘要 Various aspects of the invention are directed to memory circuits and their implementation. According to an example embodiment, an apparatus includes a channel region between raised source and drain regions which are configured and arranged with respective bandgap offsets relative to the channel region to confine carriers in the channel region. The apparatus also includes front and back gates respectively separated from the channel region by gate dielectrics. The raised source and drain regions have respective portions laterally adjacent the front gate and adjacent the channel region. Carriers are stored in the channel region via application of voltage(s) to the front and back gates, and relative to bias(es) at the source and drain regions.
申请公布号 US8969924(B2) 申请公布日期 2015.03.03
申请号 US201313774216 申请日期 2013.02.22
申请人 The Board of Trustees of the Leland Stanford Junior University 发明人 Pal Ashish;Nainani Aneesh;Saraswat Krishna Chandra
分类号 H01L29/78;H01L29/66;H01L27/108;H01L29/778;H01L29/786;H01L21/84;H01L27/12;H01L29/267 主分类号 H01L29/78
代理机构 Crawford Maunu PLLC 代理人 Crawford Maunu PLLC
主权项 1. An apparatus comprising: a front gate; a channel region below the front gate; a first gate dielectric between the front gate and the channel region; a second gate dielectric below the channel region; a back gate below the channel region and separated from the channel region by the second gate dielectric; a raised source region having respective portions laterally adjacent the front gate and adjacent the channel region; and a raised drain region having respective portions laterally adjacent the front gate, the source and drain regions being configured and arranged with the channel region to confine carriers in the channel region via respective bandgap offsets between the channel region and each of the source and drain regions.
地址 Palo Alto CA US