Receiver circuit

摘要

A receiver circuit is provided which receives an external signal of high voltage and provides a corresponding internal signal of low voltage. The receiver circuit includes a voltage limiter, a level down shifter and an inverter of low operation voltage. The level down shifter has a front node and a back node, and includes a transistor with a gate and a source respectively coupled to the voltage limiter and the inverter at the front node and the back node. The voltage limiter limits level of the external signal transmitted to the front node, the level down shifter shifts down a signal of the front node by a cross voltage to generate a signal of the back node, and the inverter inverts the signal of the back node to generate the internal signal.

主权项

1. A receiver circuit receiving an external signal and providing an internal signal in response, a swing range of the external signal corresponding to a range between a first supply voltage and a basic supply voltage, a swing range of the internal signal corresponding to a range between a second supply voltage and the basic supply voltage, the second supply voltage being lower than the first supply voltage, and the receiver circuit comprising:
an external node coupled to the external signal; a level down shifter operating between the second supply voltage and the basic supply voltage, and having a front node and a back node; the front node being coupled to the external node, and the level down shifter comprising: a main transistor having a main gate, a main drain and a main source respectively coupled to the front node, the second supply voltage and the back node; wherein when a signal of the front node reaches a logic high level, the level down shifter is capable of causing a signal of the back node to approach the second supply voltage minus a cross voltage; and an inverter operating between the second supply voltage and the basic supply voltage, being coupled to the back node, and inverting the signal of the back node to generate the internal signal; and a voltage limiter coupled between the external node and the front node, and having a first transmitting node and second transmitting node respectively coupled to the external node and the front node; wherein if the signal of the first transmitting node is lower than a reference level, the voltage limiter causes a signal of the second transmitting node to track the signal of the first transmitting node; and if the signal of the first transmitting node is higher than the reference level, the voltage limiter causes the signal of the second transmitting node to fix to a limiting level; wherein the voltage limiter comprises:
a first transistor having a first gate, a first source and a first drain, one of the first source and the first drain being coupled to the first transmitting node and the other being coupled to the second transmitting node;a second transistor having a second gate, a second source and a second drain; the second gate coupled to the second supply voltage, one of the second source and the second drain coupled to the first transmitting node and the other coupled to the first gate;a third transistor having a third gate, a third source and a third drain; the third gate coupled to the first transmitting node, one of the third source and the third drain coupled to the second supply voltage and the other coupled to the first gate; anda fourth transistor having a fourth gate, a fourth source and a fourth drain; the fourth gate coupled to the second supply voltage, one of the fourth source and the fourth drain coupled to the first transmitting node and the other coupled to the second transmitting node.