发明名称 Solution to deal with die warpage during 3D die-to-die stacking
摘要 A method including forming a contact pad array on an integrated circuit substrate, the contact pad array including a first plurality of contact pads and a second plurality of contact pads, wherein an accessible area of each of the first plurality of contact pads is different than an accessible area of each of the second plurality of contact pads; and depositing solder on the accessible area of the contact pads. An apparatus including an integrated circuit substrate including a body having a nonplanar shape and a surface including a first plurality of contact pads and a second plurality of contact pads, wherein an accessible area of each of the first plurality of contact pads is different than an accessible area of each of the second plurality of contact pads.
申请公布号 US8970051(B2) 申请公布日期 2015.03.03
申请号 US201313930889 申请日期 2013.06.28
申请人 Intel Corporation 发明人 Shi Hualiang;Ou Shengquan E.;Agraharam Sairam;Osborn Tyler N.
分类号 H01L23/52;H01L23/48;H01L23/02;H01L23/488;H01L21/44;H01L21/50;H01L21/768;H01L23/498 主分类号 H01L23/52
代理机构 Blakely, Sokoloff, Taylor & Zafman LLP 代理人 Blakely, Sokoloff, Taylor & Zafman LLP
主权项 1. A method comprising: forming a contact pad array on an integrated circuit substrate, the contact pad array comprising a first plurality of contact pads disposed on a first area of the substrate and a second plurality of contact pads disposed on a second area of the substrate, wherein a shape of the integrated circuit substrate is at least one of a convex shape or a concave shape relative to a planar surface and an accessible area of each of the first plurality of contact pads is different than an accessible area of each of the second plurality of contact pads and the accessible area is defined by a top surface and a sidewall surface; and depositing solder on the accessible area of the contact pads.
地址 Santa Clara CA US