Modifying work function in PMOS devices by counter-doping

摘要

A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode.

主权项

1. A structure comprising:
a semiconductor substrate; a first p-type transistor device in a memory region in the semiconductor substrate, the first p-type transistor device comprising a first gate electrode; and a second p-type transistor device in a peripheral circuit, the second p-type transistor device comprising a second gate electrode, wherein a work function of the first gate electrode is different from a work function of the second gate electrode, and wherein a saturation voltage of the first p-type transistor device is greater than 10% more than a saturation voltage of the second p-type transistor device.