发明名称 |
Method for manufacturing semiconductor device |
摘要 |
Described is a method for manufacturing a semiconductor device. A mask is formed over an insulating film and the mask is reduced in size. An insulating film having a projection is formed using the mask reduced in size, and a transistor whose channel length is reduced is formed using the insulating film having a projection. Further, in manufacturing the transistor, a planarization process is performed on a surface of a gate insulating film which overlaps with a top surface of a fine projection. Thus, the transistor can operate at high speed and the reliability can be improved. In addition, the insulating film is processed into a shape having a projection, whereby a source electrode and a drain electrode can be formed in a self-aligned manner. |
申请公布号 |
US8969144(B2) |
申请公布日期 |
2015.03.03 |
申请号 |
US201314062000 |
申请日期 |
2013.10.24 |
申请人 |
Semiconductor Energy Laboratory Co., Ltd. |
发明人 |
Suzawa Hideomi;Sasagawa Shinya;Ishizuka Akihiro |
分类号 |
H01L21/00;H01L21/84;H01L29/66;H01L27/12;H01L29/786;H01L21/44 |
主分类号 |
H01L21/00 |
代理机构 |
Robinson Intellectual Property Law Office, P.C. |
代理人 |
Robinson Eric J.;Robinson Intellectual Property Law Office, P.C. |
主权项 |
1. A method for manufacturing a semiconductor device comprising steps of:
forming a first conductive film over a first insulating film; forming a first mask over the first conductive film; performing a slimming process on the first mask to form a second mask; performing an etching process on the first insulating film and the first conductive film using the second mask to form a second insulating film having a projection and to form a gate electrode over a top surface of the projection of the second insulating film; forming a gate insulating film over the second insulating film and the gate electrode so as to cover the gate electrode; performing a planarization process on part of a surface of the gate insulating film which overlaps with the top surface of the projection of the second insulating film; forming an oxide semiconductor film over the gate insulating film; and forming a source electrode and a drain electrode over the oxide semiconductor film so as not to overlap with the top surface of the projection of the second insulating film. |
地址 |
Atsugi-shi, Kanagawa-ken JP |