Classifying processor testcases

摘要

Embodiments of a testcase checker system are disclosed herein. Embodiments of a testcase checker system may include an instruction set simulator configured to simulate execution of instructions of a testcase on a microprocessor using a reference model associated with an architecture of the microprocessor. The instruction set simulator may generate logging data associated with the each instruction based on the simulated execution of that instruction. The testcase checker system may also include checker module comprising a set of rules. Each of these rules may be associated with a boundedly undefined condition. The checker module is configured to receive the logging data associated with an instruction from the instruction set simulator and process the logging data based on the rules to determine if any of the rules are violated.

主权项

1. A testcase checker system, comprising:
a processor; and a computer readable medium, the computer readable medium comprising instructions to be executed by the processor, the instructions include:
an instruction set simulator configured to simulate execution of each instruction of a sequence of instructions of a testcase on a microprocessor, wherein simulating the execution of each instruction includes using a reference model associated with an architecture of the microprocessor, and to generate logging data associated with each instruction of the sequence of instructions based on the simulated execution of that instruction; anda checker module comprising a set of rules, wherein each rule is associated with a boundedly undefined condition and the checker module is configured to receive the logging data associated with each instruction from the instruction set simulator and to process the logging data associated with each instruction based on each rule to determine if each rule is violated.