Execution of a secured environment initialization instruction on a point-to-point interconnect system

摘要

Methods and apparatus for initiating secure operations in a microprocessor system are described. In one embodiment, a system includes a processor to execute a secured enter instruction, and a chipset to cause the system to enter a quiescent state during execution of the secured enter instruction.

主权项

1. A system, comprising:
a chipset including a single quiesce indicator; and a first processor of a plurality of processors coupled to a point-to-point fabric, the first processor to execute a secured enter instruction by writing to the single quiesce indicator to cause the chipset to quiesce all processors of the plurality of processors, except the first processor, during execution of the secured enter instruction, and to clear the single quiesce indicator after executing the secured enter instruction to cause the chipset to bring the system out of the quiesced state.