| 主权项 |
1. An apparatus comprising:
a pulse generator to generate a first pulse signal and a second pulse signal based on a clock signal and a test enable signal, the pulse generator generating the first pulse signal when the test enable signal is in a first state, the pulse generator generating the second pulse signal when the test enable signal is in a second state, the pulse generator comprising a delay circuit having delay components connected in series, comprising a first delay component and a second delay component, wherein each of the first and second delay components comprises a transistor of a first type and a transistor of a second type, the first type of transistor of the first delay component has a channel width that is larger than the channel width of the first type of transistor of the second delay component, and the second type of transistor of the second delay component has a channel width that is larger than the channel width of the second type of transistor of the first delay component; and a latch circuit that selectively latches one of a normal data input signal and a test data input signal, and outputs the latched signal, the latch circuit comprising a first tri-state element and a second tri-state element, the first tri-state element being controlled by the first pulse signal to enable the test data input signal to be latched when the test enable signal is in the first state, the second tri-state element being controlled by the second pulse signal to enable the normal data input signal to be latched when the test enable signal is in the second state; wherein the pulse generator is configured to generate the first and second pulse signals such that the first pulse signal has a pulse width that is different from a pulse width of the second pulse signal. |
