Array substrate and manufacturing method thereof

摘要

A manufacturing method of an array substrate includes the following steps. A gate electrode and a gate insulator layer are successively formed on a substrate. A semiconductor layer, an etching stop layer, a hard mask layer, and a second patterned photoresist are successively formed on the gate insulator layer. The second patterned photoresist is employed for performing an over etching process to the hard mask layer to form a patterned hard mask layer. The second patterned photoresist is employed for performing a first etching process to the etching stop layer. The second patterned photoresist is then employed for performing a second etching process to the semiconductor layer to form a patterned semiconductor layer. The etching stop layer uncovered by the patterned hard mask layer is then removed for forming a patterned etching stop layer.

主权项

1. A manufacturing method of an array substrate, comprising:
providing a substrate; performing a first photolithography process to form a gate electrode on the substrate; forming a gate insulating layer to cover the substrate and the gate electrode; performing a second photolithography process, wherein the second photolithography process comprises:
forming a semiconductor layer, an etching stop layer and a hard mask layer on the gate insulating layer successively, and forming a second patterned photoresist on the hard mask layer;employing the second patterned photoresist for performing an over etching process to the hard mask layer to form a patterned hard mask layer on the etching stop layer;employing the second patterned photoresist for performing a first etching process to the etching stop layer;employing the second patterned photoresist for performing a second etching process to the semiconductor layer to form a patterned semiconductor layer on the gate insulating layer; andremoving the etching stop layer uncovered by the patterned hard mask layer for forming a patterned etching stop layer on the patterned semiconductor layer; and performing a third photolithography process to form a source electrode and a drain electrode on the patterned etching stop layer and the patterned semiconductor layer.