发明名称 |
System and method for functional verification of multi-die 3D ICs |
摘要 |
A system and method is disclosed for functional verification of multi-die 3D ICs. The system and method include a reusable verification environment for testing each die in a stack of dies individually without having to simultaneously operate all of the dies in the stack. The system and method includes converting an input/output (“IO”) trace from a die verification test from a first format to a second format to improve performance. |
申请公布号 |
US8972918(B2) |
申请公布日期 |
2015.03.03 |
申请号 |
US201213359921 |
申请日期 |
2012.01.27 |
申请人 |
Taiwan Semiconductor Manufacturing Co. Ltd. |
发明人 |
John Stanley;Mehta Ashok;Goel Sandeep Kumar;Ting Kai-Yuan |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
Duane Morris LLP |
代理人 |
Duane Morris LLP |
主权项 |
1. A method for verifying a functionality of ones of a plurality of dies arranged in a stack of dies, the method comprising the steps of:
(a) operatively connecting a first die of said plural dies to a test bench external to the stack of dies and to a first peripheral module external to the stack of dies; (b) verifying a functionality of said first die to thereby produce a first input/output (“IO”) trace in a first format, wherein said first format is a signal level format; (c) disconnecting said first die from said test bench; (d) translating said first IO trace in the first format to a first IO trace in a second format, wherein said second format is a transaction level format; (e) operatively connecting a second die of said plural dies to said test bench and to a second peripheral module; (f) applying said first IO trace in the second format to said test bench; and (g) verifying a functionality of said second die via said first IO trace in the second format by using said test bench. |
地址 |
Hsin-Chu TW |