发明名称 |
Defective P-N junction for backgated fully depleted silicon on insulator MOSFET |
摘要 |
Methods for semiconductor fabrication include forming a well in a semiconductor substrate. A pocket is formed within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket. Defects are created at the p-n junction such that a leakage resistance of the p-n junction is decreased. |
申请公布号 |
US8969966(B2) |
申请公布日期 |
2015.03.03 |
申请号 |
US201313866077 |
申请日期 |
2013.04.19 |
申请人 |
International Business Machines Corporation;STMicroelectronics, Inc.;Commissariat a l'Energie Atomique et aux Energies Alternatives |
发明人 |
Cheng Kangguo;Doris Bruce B.;Grenouillet Laurent;Khakifirooz Ali;Le Tiec Yannick;Liu Qing;Vinet Maud |
分类号 |
H01L21/336;H01L21/761;H01L29/06;H01L29/66;H01L29/786 |
主分类号 |
H01L21/336 |
代理机构 |
Tutunjian & Bitetto, P.C. |
代理人 |
Tutunjian & Bitetto, P.C. ;Alexanian Vazken |
主权项 |
1. A method for semiconductor fabrication, comprising:
forming a well in a semiconductor substrate, the semiconductor substrate including a semiconductor on insulator (SOI) layer present on a buried dielectric layer, the buried dielectric layer being present on a base semiconductor layer, wherein the well region is present within the base semiconductor layer; forming a pocket within the well region directly underlying the buried dielectric layer, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket; creating defects at the p-n junction such that a leakage resistance of the p-n junction is decreased. |
地址 |
Armonk NY US |