发明名称 |
Electronic endoscopic apparatus |
摘要 |
An electronic endoscopic apparatus includes an endoscopic scope and an image processing processor. The endoscopic scope includes a solid-state imaging device, an imaging-side multiplying unit, and an imaging synchronization signal generating unit. The image processing processor includes a display clock generating unit, a monitor synchronization signal generating unit, a master imaging clock generating unit, a processor-side multiplying/dividing unit, a phase-comparison oscillation control unit, and a display timing adjustment unit. |
申请公布号 |
US8970686(B2) |
申请公布日期 |
2015.03.03 |
申请号 |
US201213547711 |
申请日期 |
2012.07.12 |
申请人 |
Olympus Corporation |
发明人 |
Kobayashi Naruyasu;Kotoda Kaoru;Nishimura Hisashi;Azuma Motoo;Takizawa Kazuhiro;Sato Takayuki;Tanaka Satoshi |
分类号 |
H04N7/18;H04N5/06;A61B1/00;A61B1/045;G09G5/12;G09G5/00 |
主分类号 |
H04N7/18 |
代理机构 |
Westerman, Hattori, Daniels & Adrian, LLP |
代理人 |
Westerman, Hattori, Daniels & Adrian, LLP |
主权项 |
1. An electronic endoscopic apparatus comprising:
an endoscopic scope; and an image processing processor, wherein the endoscopic scope comprises: a solid-state imaging device is configured to convert optical information to an electrical signal, and is configured to output the electrical signal as an image signal; an imaging-side multiplying unit is configured to generate a scope-side multiplication clock by multiplying a transmission imaging clock input from the image processing processor; and an imaging synchronization signal generating unit is configured to generate an imaging synchronization signal for driving the solid-state imaging device from the scope-side multiplication clock; and the image processing processor comprises: a display clock generating unit is configured to generate a display clock; a monitor synchronization signal generating unit is configured to generate a monitor synchronization signal based on the display clock; a master imaging clock generating unit is configure to generate an master imaging clock; a processor-side multiplying/dividing unit is configured to generate a process-side imaging clock obtained by converting the master imaging clock, and is configured to generate a transmission imaging clock obtained by converting the master imaging clock; a phase-comparison oscillation control unit is configured to compare the phases of the monitor synchronization signal and the processor-side imaging clock, and controls the oscillation of the master imaging clock generating unit based on the result of that comparison; and a display timing adjustment unit is configured to use the imaging synchronization signal, the processor-side imaging clock, the monitor synchronization signal, and the display clock, and is configured to output the image signal in synchrony with the monitor synchronization signal. |
地址 |
Tokyo JP |