Ultra low-power pipelined processor

摘要

A pipelined processor including a combinational logic of several stages, a voltage regulator, a counter, a comparator, and a plurality of stage registers. Each stage register is disposed between two adjacent stages of the combinational logic. The stage register includes a flip-flop, a latch, an XOR gate, and a MUX module. When the high level of a register clock is coming, the flip-flop latches first data at the rising edge, and the latch receives second data during the high level. The data latched by the flip-flop and the latch respectively are compared by the XOR gate. If they are same, the output Error of the XOR gate is low level, and the output of the flip-flop is delivered to the next stage. Otherwise, the output Error of the XOR gate is high level, and the output of the latch is delivered to the next stage.

主权项

1. A pipelined processor, comprising:
a) a combinational logic of several stages; b) a voltage regulator; c) a counter; d) a comparator; and e) a plurality of stage registers, said stage registers being double latch (DL) registers and each being disposed between two adjacent stages of said combinational logic; wherein said DL register comprises a flip-flop, a latch, an XOR gate, and a MUX module; when a high level of a register clock CLK1 is coming, said flip-flop latches first data at the rising edge, and said latch receives second data during the high level of said register clock CLK1; said data, latched by said flip-flop and said latch respectively, are compared by said XOR gate: if they are same, an output Error of said XOR gate is low level, and an output A of said flip-flop is delivered to a next stage; if they are different, the output Error of said XOR gate is high level, and an output B of said latch is delivered to the next stage; the output Error of a last DL register is inverted, then AND with a clock CLK of said processor to obtain said register clock CLK1, and meanwhile, the rising edge of the output Error is used to count said counter; and the result E—sample of said counter in a count cycle is compared with a reference error number E—ref by said comparator: if E—sample>E—ref, the result E—diff of said comparator controls said voltage regulator to augment the supply voltage of said processor; if E—sample