Level shifter, system-on-chip including the same, and multimedia device including the same

摘要

Disclosed is a level shifter that includes an input node; first and second voltage shifter circuits configured to generate an output clock of a second voltage domain in response to an input clock of a first voltage domain input via the input node, and an output node configured to output the output clock, wherein the first and second voltage shifter circuits have the same structure and are connected in parallel between the input node and an output node.

主权项

1. A level shifter, comprising:
an input node; a voltage shifter connected between the input node and configured to generate an output clock of a second voltage domain in response to an input clock of a first voltage domain input via the input node; and an output node connected to the shifter and configured to output the output clock, wherein the voltage shifter includes a first voltage shifter circuit and a second voltage shifter circuit having a same structure and connected in parallel between the input node and the output node, wherein the first voltage shifter circuit includes at least two inverters operating at the second voltage domain, the at least two inverters directly connected in series between the input node and the output node, and wherein the second voltage shifter circuit includes at least one first inverter operating at the first voltage domain and at least one second inverter operating at the second voltage domain, wherein the at least one first inverter and the at least one second inverter are directly connected in series between the input node and the output node.