DC Offset Correction with Low Frequency Signal Support Circuits and Methods

摘要

DC offset correction is provided with low frequency support. A first input terminal for receiving an input signal is selectively coupled to a resistance and a capacitor that are series coupled between the first input terminal and a corresponding output terminal. In a calibration phase, the series resistance is coupled between the input terminal and the capacitor and an average voltage level of the input is stored on capacitor. In a signal processing phase, the charged capacitor is coupled in series between the input terminal and the output terminal while the resistance is bypassed. The output signal obtained contains the high and low frequency components of the input signal, while the DC offset in the input signal is removed from the output signal. A differential circuit and methods are disclosed. Additional embodiments are disclosed.

主权项

1. A DC offset correction circuit, comprising:
a first input terminal for receiving an input signal; a first resistance selectively coupled in series to the first input terminal, responsive to a calibration enable signal; and a first capacitor selectively coupled in series to the first resistance responsive to the calibration enable signal, the first capacitor alternatively selectively coupled between the first input terminal and a first output terminal while the first resistance is bypassed, responsive to a signal processing signal.